1. Technical Field
The present invention relates to data communication networking devices, more particularly, to modifying the digital registers associated with the different functions of a network switch without changing the source code.
2. Background Art
In computer networks, a plurality of network stations are interconnected via a communications medium. For example, Ethernet is a commonly used local area network scheme in which multiple stations are connected to a single shared serial data path. These stations often communicate with a switch located between the shared data path and the stations connected to that path. Typically, the switch controls the communication of data packets on the network.
The design of such a complex switch entails testing and managing a multitude of components, using a variety of design tools. Among the components that are vital to the switch""s operation are its internal registers, which are used to store and process various digital signals. A bit definition table defines each of the bits within a register as welt as predesignated default values. In a conventional design approach, the bit definition table is modified (i.e., updated) and utilized by a number of switch design teams (e.g., hardware design team and test and evaluation team). For example, the hardware design team relies on the bit definition table to produce a schematic of the actual components to implement the registers. The bit definition table is also needed by a test and evaluation team to develop test cases for ensuring the proper operation of the registers within the switch.
Typically, the design parameters of the digital registers are maintained separately and updated in an ad hoc fashion by the respective design teams. One conventional approach is shown in FIG. 5, which is a flow diagram of the design process involving a hardware design team and a test and evaluation team. In this exemplary process, it is assumed that the hardware design team in charge of a source code compiler, which synthesizes the hardware components of the multiport switch, seeks to change a register design parameter (step 501). In step 503, the hardware design team manually enters the new design parameter into the RTL (Register Transfer Level) code, which is processed by the source code compiler. Next, the source code compiler, in step 505, performs hardware synthesis of the source code; in this step, the source code is converted by the source code compiler into a hardware schematic (step 507).
Concurrently, the test and evaluation team also utilizes the modified design parameters, which is typically captured in a technical document. The test and evaluation team then manually enters the modified design parameter into the test bench, per step 509. The modified register design is used, as in step 511, to develop new test cases, which seek to test all the functions of the corresponding digital registers in an operation mode within the multiport switch. The next step 513 involves the test and evaluation team performing hardware verification of the digital registers. In turn, the test bench runs a series of simulations and outputs the simulation results per step 515. In step 517, the simulation results are examined to determine whether they are satisfactory; that is, the modified digital registers are operating within the multiport switch according to pre-established design criteria. In the event that the simulation results fall outside the established criteria, the modified digital registers are not implemented. However, if the simulation results are satisfactory, the digital registers as modified are implemented per step 519.
As illustrated in FIG. 5, for complex systems such as a network switch, numerous design teams (in this case, two design teams) work cooperatively to develop and test the switch. As a result, when one design team modifies design parameters, the other teams may not be aware of the changes until after the development efforts have occurred. That is, design mismatch due to version or interpretation errors is problematic. Another concern is that each design team must manually update source code variables or test bench inputs with the modified design parameters, thereby increasing the chances of coding errors. This also increases development time and costs.
There exists a need for a centrally storing and maintaining the design parameters of the digital registers to coordinate the updating of the implementation of the registers to avoid design mismatch. There is also a need for automatically modifying the register design parameters to eliminate coding errors to improve the efficiency of the design process.
These and other needs are met by the present invention, where design parameters associated with the digital registers of the network switch are maintained and stored in a central storage medium. These design parameters are automatically read into the source code, whereby the values and definitions of the registers are modified without altering the source code.
One aspect of the present invention provides a method for modifying the design of a digital register in a network switch. The method comprises modifying the design parameters associated with the digital register. The design parameters includes bit definition and bit default values. The method also includes centrally storing the modified design parameters in a central database and retrieving the modified design parameters from the central database into a source code that specifies functionality of the digital register within the multiport switch to initialize and define corresponding code variables within the source code. Hardware synthesis is performed based upon the modified design parameters. The method further comprises performing hardware verification based upon the modified design parameters. Lastly, the modified digital register is implemented in the network switch. Under this arrangement, the source code pertaining to the registers does not need to be modified, thereby advantageously reducing development time.
According to another aspect of the invention, a system for modifying the design of digital registers of a network switch comprises a centralized data storage system for storing and updating a register table that comprises a plurality of entries associated with the digital registers. Each of the register table entries includes bit definition and bit default values corresponding to each of the digital registers. A source code compiler has hardware modeling capability configured for importing entries from the centralized data storage system and initializing and defining corresponding code variables, and outputting a hardware schematic diagram of the digital register. A testing device is configured for concurrently testing operation and functionality of the digital registers based upon the register table entries. Accordingly, the source code can be automatically updated; thus, reducing the possibility of coding errors due to manual updates.
In yet another aspect of the invention, a system for modifying design of digital registers of a network switch comprises a central database for storing design parameters associated with the digital registers. A source code compiler retrieves the design parameters and utilizes the design parameters in a first procedure. In addition, a testing device retrieves the design parameters and utilizes the design parameters in a second procedure. This system provides for an efficient way to modify the design parameters of digital registers within a network switch and to reduce data entry errors.
Additional advantages and novel features of the invention will be set forth in part in the description which follows, and in part may become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.